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features description/ordering information sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 member of the texas instruments widebus? family operates from 1.65 v to 3.6 v inputs accept voltages to 5.5 v max t pd of 4.5 ns at 3.3 v typical v olp (output ground bounce) <0.8 v at v cc = 3.3 v, t a = 25 c typical v ohv (output v oh undershoot) >2 v at v cc = 3.3 v, t a = 25 c i off supports partial-power-down mode operation supports mixed-mode signal operation on all ports (5-v input and output voltages with 3.3-v v cc ) bus hold on data inputs eliminates the need for external pullup/pulldown resistors latch-up performance exceeds 250 ma per jesd 17 esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 1000-v charged-device model (c101) this 16-bit edge-triggered d-type flip-flop is designed for 1.65-v to 3.6-v v cc operation. ordering information t a package (1) orderable part number top-side marking fbga ? grd sn74lvch16374agrdr tape and reel ldh374a fbga ? zrd (pb-free) sn74lvch16374azrdr sn74lvch16374adl tube 74lvch16374adlg4 ssop ? dl lvch16374a sn74lvch16374adl tape and reel 74lvch16374adlrg4 ?40 c to 85 c sn74lvch16374adggr tssop ? dgg tape and reel lvch16374a 74lvch16374adggrg4 sn74lvch16374adgvr tvsop ? dgv tape and reel ldh374a 74lvch16374adgvre4 vfbga ? gql sn74lvch16374agqlr tape and reel ldh374a vfbga ? zql (pb-free) SN74LVCH16374AZQLR (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2003?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com dgg, dgv , or dl p ackage (t op view) 12 3 4 5 6 7 8 9 10 1 1 1213 14 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1oe 1q11q2 gnd 1q31q4 v c c 1q51q6 gnd 1q71q8 2q1 2q2 gnd 2q32q4 v c c 2q52q6 gnd 2q72q8 2oe 1clk1d1 1d2 gnd 1d3 1d4 v c c 1d51d6 gnd 1d7 1d8 2d1 2d2 gnd 2d3 2d4 v c c 2d52d6 gnd 2d7 2d8 2clk
description/ordering information (continued) sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 a buffered output-enable ( oe) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect internal operations of the flip-flop. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. inputs can be driven from either 3.3-v or 5-v devices. this feature allows the use of this device as a translator in a mixed 3.3-v/5-v system environment. active bus-hold circuitry holds unused or undriven inputs at a valid logic state. use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. the sn74lvch16374a is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. it can be used as two 8-bit flip-flops or one 16-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels set up at the data (d) inputs. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. terminal assignments (1) (56-ball gql/zql package) 1 2 3 4 5 6 a 1 oe nc nc nc nc 1clk b 1q2 1q1 gnd gnd 1d1 1d2 c 1q4 1q3 v cc v cc 1d3 1d4 d 1q6 1q5 gnd gnd 1d5 1d6 e 1q8 1q7 1d7 1d8 f 2q1 2q2 2d2 2d1 g 2q3 2q4 gnd gnd 2d4 2d3 h 2q5 2q6 v cc v cc 2d6 2d5 j 2q7 2q8 gnd gnd 2d8 2d7 xxx k 2 oe nc nc nc nc 2clk (1) nc ? no internal connection terminal assignments (1) (54-ball grd/zrd package) 1 2 3 4 5 6 a 1q1 nc 1 oe 1clk nc 1d1 b 1q3 1q2 nc nc 1d2 1d3 c 1q5 1q4 v cc v cc 1d4 1d5 d 1q7 1q6 gnd gnd 1d6 1d7 e 2q1 1q8 gnd gnd 1d8 2d1 f 2q3 2q2 gnd gnd 2d2 2d3 g 2q5 2q4 v cc v cc 2d4 2d5 h 2q7 2q6 nc nc 2d6 2d7 j 2q8 nc 2 oe 2clk nc 2d8 (1) nc ? no internal connection 2 www .ti.com gql or zql p ackage (t op view) j h g f e d c b a 2 1 3 4 6 5 k grd or zrd p ackage (t op view) j h g f e d c b a 2 1 3 4 6 5
absolute maximum ratings (1) sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 function table (each flip-flop) inputs output q oe clk d l - h h l - l l l h or l x q 0 h x x z logic diagram (positive logic) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ?0.5 6.5 v v i input voltage range (2) ?0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ?0.5 6.5 v v o voltage range applied to any output in the high or low state (2) (3) ?0.5 v cc + 0.5 v i ik input clamp current v i < 0 ?50 ma i ok output clamp current v o < 0 ?50 ma i o continuous output current 50 ma continuous current through each v cc or gnd 100 ma dgg package 70 dgv package 58 q ja package thermal impedance (4) dl package 63 c/w gql/zql package 42 grd/zrd package 36 t stg storage temperature range ?65 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. (4) the package thermal impedance is calculated in accordance with jesd 51-7. 3 www .ti.com 1oe 1clk 1d1 t o seven other channels 1q1 2oe 2clk 2d1 2q1 t o seven other channels 148 47 2425 36 c1 1d 13 2 c1 1d pin numbers shown are for the dgg, dgv , and dl packages.
recommended operating conditions (1) sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 min max unit operating 1.65 3.6 v cc supply voltage v data retention only 1.5 v cc = 1.65 v to 1.95 v 0.65 v cc v ih high-level input voltage v cc = 2.3 v to 2.7 v 1.7 v v cc = 2.7 v to 3.6 v 2 v cc = 1.65 v to 1.95 v 0.35 v cc v il low-level input voltage v cc = 2.3 v to 2.7 v 0.7 v v cc = 2.7 v to 3.6 v 0.8 v i input voltage 0 5.5 v high or low state 0 v cc v o output voltage v high-impedance state 0 5.5 v cc = 1.65 v ?4 v cc = 2.3 v ?8 i oh high-level output current ma v cc = 2.7 v ?12 v cc = 3 v ?24 v cc = 1.65 v 4 v cc = 2.3 v 8 i ol low-level output current ma v cc = 2.7 v 12 v cc = 3 v 24 d t/ d v input transition rise or fall rate 10 ns/v t a operating free-air temperature ?40 85 c (1) all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. 4 www .ti.com
electrical characteristics timing requirements sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit i oh = ?100 m a 1.65 v to 3.6 v v cc ? 0.2 i oh = ?4 ma 1.65 v 1.2 i oh = ?8 ma 2.3 v 1.7 v oh v 2.7 v 2.2 i oh = ?12 ma 3 v 2.4 i oh = ?24 ma 3 v 2.2 i ol = 100 m a 1.65 v to 3.6 v 0.2 i ol = 4 ma 1.65 v 0.45 v ol i ol = 8 ma 2.3 v 0.7 v i ol = 12 ma 2.7 v 0.4 i ol = 24 ma 3 v 0.55 i i v i = 0 to 5.5 v 3.6 v 5 m a v i = 0.58 v (2) 1.65 v v i = 1.07 v (2) v i = 0.7 v 45 2.3 v i i(hold) v i = 1.7 v ?45 m a v i = 0.8 v 75 3 v v i = 2 v ?75 v i = 0 to 3.6 v (3) 3.6 v 500 i off v i or v o = 5.5 v 0 10 m a i oz v o = 0 to 5.5 v 3.6 v 10 m a v i = v cc or gnd 20 i cc i o = 0 3.6 v m a 3.6 v v i 5.5 v (4) 20 d i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd 2.7 v to 3.6 v 500 m a c i v i = v cc or gnd 3.3 v 5 pf c o v o = v cc or gnd 3.3 v 6.5 pf (1) all typical values are at v cc = 3.3 v, t a = 25 c. (2) this information was not available at the time of publication. (3) this is the bus-hold maximum dynamic current required to switch the input from one state to another. (4) this applies in the disabled state only. over recommended operating free-air temperature range (unless otherwise noted) (see figure 1 ) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v 0.15 v 0.2 v 0.3 v unit min max min max min max min max f clock clock frequency (1) (1) 150 150 mhz t w pulse duration, clk high or low (1) (1) 3.3 3.3 ns t su setup time, data before clk - (1) (1) 1.9 1.9 ns t h hold time, data after clk - (1) (1) 1.1 1.1 ns (1) this information was not available at the time of publication. 5 www .ti.com
switching characteristics operating characteristics sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 over recommended operating free-air temperature range (unless otherwise noted) (see figure 1 ) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v from to 0.15 v 0.2 v 0.3 v parameter unit (input) (output) min max min max min max min max f max (1) (1) 150 150 mhz t pd clk q (1) (1) (1) (1) 4.9 1.5 4.5 ns t en oe q (1) (1) (1) (1) 5.3 1.5 4.6 ns t dis oe q (1) (1) (1) (1) 6.1 1.5 5.5 ns t sk(o) 1 ns (1) this information was not available at the time of publication. t a = 25 c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v test parameter unit conditions typ typ typ outputs enabled (1) (1) 58 power dissipation capacitance c pd f = 10 mhz pf per flip-flop outputs disabled (1) (1) 24 (1) this information was not available at the time of publication. 6 www .ti.com
parameter measurement information sn74lvch16374a 16-bit edge-triggered d-type flip-flop with 3-state outputs scas757a ? december 2003 ? revised october 2005 figure 1. load circuit and voltage waveforms 7 www .ti.com v m t h t s u from output under t est c l (see note a) load circuit s1 v l o a d open gnd r l r l data input t iming input v i 0 vv i 0 v 0 v t w input vol t age w a veforms setup and hold times vol t age w a veforms prop aga tion dela y times inverting and noninverting outputs vol t age w a veforms pulse dura tion t p l h t p h l t p h l t p l h v o h v o h v o l v o l v i 0 v input output w aveform 1 s1 at v l o a d (see note b) output w aveform 2 s1 at gnd (see note b) v o l v o h t p z l t p z h t p l z t p h z v l o a d /2 0 v v o l + v d v o h ? v d 0 v v i vol t age w a veforms enable and disable times low - and high-level enabling outputoutput t p l h /t p h l t p l z /t p z l t p h z /t p z h open v l o a d gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w . d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . h. all parameters and waveforms are not applicable to all devices. output control v m v m v m v m v m v m v m v m v m v m v m v m v i v m v m 1.8 v 0.15 v 2.5 v 0.2 v 2.7 v 3.3 v 0.3 v 1 k w 500 w 500 w 500 w v c c r l 2 v c c 2 v c c 6 v6 v v l o a d c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d v c c v c c 2.7 v2.7 v v i v c c /2 v c c /2 1.5 v1.5 v v m t r /t f 2 ns 2 ns 2.5 ns 2.5 ns inputs
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 74lvch16374adggrg4 active tssop dgg 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74lvch16374adgvre4 active tvsop dgv 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74lvch16374adlg4 active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74lvch16374adlrg4 active ssop dl 48 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvch16374adggr active tssop dgg 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvch16374adgvr active tvsop dgv 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvch16374adl active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvch16374adlr active ssop dl 48 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvch16374agqlr active bga mi crosta r juni or gql 56 1000 tbd snpb level-1-240c-unlim SN74LVCH16374AZQLR active bga mi crosta r juni or zql 56 1000 green (rohs & no sb/br) snagcu level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 18-jul-2006 addendum-page 1
in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-jul-2006 addendum-page 2

mechanical data mpds006c february 1996 revised august 2000 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194

mechanical data msso001c ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 dl (r-pdso-g**) plastic small-outline package 4040048 / e 12/01 48 pins shown 56 0.730 (18,54) 0.720 (18,29) 48 28 0.370 (9,40) (9,65) 0.380 gage plane dim 0.420 (10,67) 0.395 (10,03) a min a max 0.010 (0,25) pins ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) seating plane 0.020 (0,51) 0.040 (1,02) 25 24 0.008 (0,203) 0.0135 (0,343) 48 1 0.008 (0,20) min a 0.110 (2,79) max 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) m 0.005 (0,13) 0.025 (0,635) 0 ? 8 0.005 (0,13) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec mo-118
mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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